1. Field of the Invention
This invention relates generally to semiconductor processing, and more particularly to an integrated circuit utilizing both sides of a given wafer and to a method of making the same.
2. Description of the Related Art
The silicon wafer has long been a substrate of choice for designers of semiconductor fabrication processes. Although the earliest solid state electronic circuits utilized germanium as a semiconducting substrate material, designers soon recognized that silicon, with its larger bandgap and more reliably formable oxide for passivation, provided a superior semiconductor processing material. The switch to silicon stemmed from economic as well as technical considerations. At about a tenth of the cost of germanium, electronic grade silicon enabled manufacturers to dramatically reduced manufacturing costs for solid state circuits. Integrated circuits that were formerly affordable only to the military or the space program could be fabricated cheaply enough to be incorporated into components affordable to ordinary consumers.
The starting point in the process of fabricating an integrated circuit on silicon for most applications is the formation of a silicon wafer. Initially, an ingot of monocrystalline silicon is drawn from a vat of molten silicon and cooled. The ingot is then subjected to a sequence of shaping and polishing steps that include the grinding of the ingot to the desired diameter, the grinding of one or more of flats into the exterior of the ingot, and finally the sawing of individual wafers from of the ingot. Each of the individual wafers is then put through a variety of diagnostic tests to determine the extent of any crystalline or other structural defects. If free of significant defects, each wafer is then lapped and ground to within a specified thickness tolerance and etched to remove any work damage caused by the various sawing, lapping and grinding steps. Finally, one side of each wafer is subjected to a chemical-mechanical polishing ("CMP") step to produce a highly reflective, scratch and damage free surface upon which the integrated circuits will be formed.
In conventional semiconductor processing, integrated circuits are implemented on only one side of a given wafer. This historical use of only about one half of the available surface area of a given wafer is the product of two major processing considerations. First, wafer handling is generally a simpler task when one side of a given wafer may be repeatedly touched by various wafer handling equipment without risk of damaging the front or circuit side of the wafer. During a typical conventional process flow, a given wafer is repeatedly picked up, transported, placed into and taken out of various tools, such as chemical vapor deposition ("CVD") reactors, etch reactors, and ion implantation tools. Many of these types of tools incorporate carriers that are specifically designed to receive the relatively flat back side of the wafer. Second, the backside of the conventional wafer is often intentionally left in a relatively rough condition to facilitate extrinsic gettering of impurities. In some conventional fabrication processes, the surface variations following initial slicing and lapping are deemed sufficient. In others, additional mechanical damage is done to the backside by abrasion, grooving or sandblasting to create stress fields on the back side. During subsequent annealing steps, dislocations are generated which relieve these stress fields. These dislocations then serve as gettering sites. Although intrinsic gettering techniques have been developed as an alternative to extrinsic gettering, such as tailoring the oxygen distribution in the wafer, single-sided processing remains the norm.
A key disadvantage associated with conventional integrated circuit fabrication is the less than optimal utilization of both materials and manufacturing time. Since only one side of a given wafer is utilized for circuit implementation, less than half of the theoretical substrate area is actually devoted to circuit fabrication. In addition, nearly every process step to fabricate circuits on a conventional wafer is performed at less than optimum efficiency since only one side of each wafer in a given batch of wafers is actually being processed during the step. For example, in a typical batch dry etching process, a plurality of wafers are positioned in an etch reactor and a volume of etch gas or gases is introduced into the etch chamber. At the conclusion of the etch process, the etch mixture is exhausted from the etch reactor and discarded. The same quantity of etch gases could have been used to etch both sides of the batch of wafers without significant decrease in throughput. However, since only one side of each wafer is etched, a significant quantity of the etch gases are essentially wasted. The same applies to various other process steps, such as the CVD of dielectrics and sputter deposition of metals to name a few. Aside from the considerations of materials utilization, manufacturing time in conventional single-sided wafer processing is less than optimal. For example, the movement of a batch of conventional single-sided wafers into and out of an etch tool requires a finite quantity of time. This quantity of time is dependent on the sheer number of wafers being moved and not on the amount of each wafer that is being processed. In other words, the same amount of time is required for the movement of the batch whether ten, fifty or one hundred percent of the useable surface areas of the wafers are being processed. In conventional processing, this quantity of time is devoted to only about one half of the theoretically useable wafer surface area. However, if both sides of the wafers could be processed, that is, circuits could be fabricated on both sides, the same quantity of time could be devoted to the example movement with approximately twice the effective throughput.
The foregoing example of the movement of wafers into and out of an etch tool is just one simple example. In a typical conventional process flow, a given wafer is picked up, moved, loaded and unloaded scores of times. The underutilization of manufacturing time is cumulative of all of these various movements.
The present invention is directed to overcoming or reducing the effects of one or more of the foregoing disadvantages.